Analog Chip/ASIC Design Engineer

The Metrosert Applied Research Centre (ARC) is looking for a highly motivated and experienced Analogue Chip/ASIC Design Engineer to join our integrated circuit design team. In this role, you will be responsible for the design, simulation, verification, and layout of high-performance analogue and mixed-signal integrated circuits for ASIC applications. You’ll work closely with digital designers, layout engineers, and system architects to deliver silicon solutions that meet strict power, performance, and area requirements.

🚀 Key Responsibilities: 

• Design and develop analogue and mixed-signal circuits including (but not limited to):

  • Op-amps, comparators, ADCs/DACs, LDOs, bandgap references, PLLs, charge pumps, and oscillators;

• Own the integration of analogue and digital blocks into the top-level layout;

• Drive the final GDSII generation and handoff to the foundry;

• Perform schematic design, behavioural modelling, and circuit simulation using tools such as Spectre, HSPICE, or Eldo;

• Lead transistor-level design and oversee physical layout with a focus on parasitic effects and DRC/LVS compliance;

• Conduct design verification, including corner analysis, Monte Carlo simulations, and post-layout simulation;

• Collaborate with system and digital designers to define interface and co-design requirements;

• Support silicon bring-up, lab testing, and first silicon characterisation;

• Document design specifications, test plans, and results throughout the development process.

⭐ Qualifications:

• Bachelor’s or Master’s degree in Electrical Engineering or a related field (PhD preferred for advanced roles);

• 3+ years of experience in analogue or ASIC design (entry-level candidates may be considered with strong academic or internship background);

• Proficiency with analogue design tools such as Cadence Virtuoso, Spectre, and mixed-signal simulation environments;

• Strong understanding of CMOS technology, including noise analysis, matching, and layout-dependent effects

  ;

• Familiarity with EDA tools for layout verification and parasitic extraction (e.g. Calibre, Assura)

  ;

• Experience with scripting languages like Python, TCL, or Skill for design automation.

  Preferred Skills:

• Experience in low-power design techniques, high-voltage, automotive, or RF design;

• Hands-on experience with lab equipment such as oscilloscopes, VNAs, and SMUs for chip validation;

• Understanding of the tape-out process and experience with multi-project wafer (MPW) runs or production-level ASICs.

💡We offer you: 

• A unique opportunity to contribute to cutting-edge innovation in chip technology;

• Professional growth and self-development opportunities within a rapidly growing Applied Research Centre;

• A collaborative and supportive work environment that values teamwork, knowledge-sharing, and collective success;

• A comprehensive benefits package, including health and accident insurance, sports compensation, and support for important personal milestones.